BCM8702 ? serial 10-gigabit ethernet tr ansceiver with xaui interface BCM8702 application block diagram ? ieee 802.3ae compliant support for xenpak and xgp standards xenpak support optimized for xenpak/xgp layout and thermal fully integrated cmu, cdr, and serdes pmd interface with serial 10.3125 gbps cml psc 64b/66b scrambler/descrambler xgxs 8b/10b error detection endec xaui link synchronization/deskew four-lane, 3.125-gbps xaui interface loss-of-signal detection loopback modes 802.3 clause 45 management interface extended indirect address access built-in self-test (bist) built-in jitter tests for xaui and pmd eeprom interface support power supplies: core, lvpecl, cml, and xaui at 1.8v, mdio at 1.2v, and cmos at 1.8 or 3.3v. low power consumption eliminates external heat sinks, fans for system airflow, and expensive high current power supplies. reduces design cycle and time to market. uses the most effective silicon economy of scale for cmos- based devices. features summary of benefits lan/wan switches switch/router backbones hubs and repeaters network interface cards (nics) test equipment applications media access controller interface mac rs xgxs xgxs management interface xaui 3.125 gbps BCM8702 pcs/pma mdc mdio otx orx optical pmd eeprom 10.3125 gbps
overview ? phone: 949-450-8700 fax: 949-450-8710 e-mail: info@broadcom.com web: www.broadcom.com broadcom corporation 16215 alton parkway, p.o. box 57013 irvine, california 92619-7013 ? 2004 by broadcom corporation. all rights reserved. 8702-pb04-r 04/30/04 broadcom ? , the pulse logo, and connecting everything ? are trademarks of broadcom corporation and/ or its subsidiaries in the united states and certain other countries. all other trademarks mentioned are the property of their respective owners. the BCM8702 ethernet lan phy is a fully integrated serialization/ deserialization (10.3125 gbps) interface device performing the extension functions for a 10.3125 gbps serial ethernet reconciliation sublayer (rs) interface. the xgxs, pcs, and pma functions include 8b/10b coding, 64b/66b coding, serdes, clock multiplication unit (cmu), and clock and data recovery (cdr). on-chip clock synthesis is performed by the high-frequency, low-jitter, phase-locked loops for the pmd and xaui output retimers. individual pmd and xaui clock recovery is performed on the device by synchronizing the on-chip vcos dir ectly to their respective incoming data streams. elastic buffers allow the xaui and pmd interfaces to operate in either a synchronous or asynchronous configuration. an external 156.25- mhz vcxo is required for synchronous mode operation or for asynchronous mode with clock cleanup. the BCM8702 is packaged in a 19 x 19 x 1.86 mm bga with a 1-mm ball pitch. pcdrlk plosb xaop xaon xdop xdon xextclkp xextclkn xpdout xplllk pextclkp pextclkn ppdout pplllk pvcoxp pvcoxn xaip xain xdip xdin rstb mdc mdio phyad[4:0] sysrst txon/off trst jtck tms tdi tdo 3.125 gbps differential xaui ac-coupled differential lvpecl 156.25 mhz ac-coupled 3.125 gbps differential xaui pdip pdin pdop pdon pcop pcon optxenb optxrst optxalarm oprxalarm oprxlos optxflt opoutlvl opinlvl ac-coupled 10.3125 gbps differential cml 10.3125 gbps differential cml 10.3125 ghz differential cml serializer serializer 8b/10b encoder 8b/10b encoder cmu randomizer elastic fifo elastic fifo 64b/66b synchronizer descrambler decoder gearbox gearbox cdr & deserializer clock management cdr & deserializer cdr & deserializer sync detect lane sync 8b/10b decoder sync detect lane sync 8b/10b decoder lane alignment fifo lane alignment fifo 64b/66b encoder scrambler cmu & serializer receive path transmit path optics control and status eprom interface controls management registers jtag sda scl
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